§ Products
AI compute, scalable.
From 0.25–0.5 TOPS always-on sensing to 33 TOPS heterogeneous compute — same unified Alp SDK, same C/C++ API, same toolchain. Pick the AI power you need today; swap modules without rewriting a line of code when you scale.
§ AI compute ladder
log scale · TOPS
range
0.25–0.5 TOPS → 33 TOPS
§ All modules · ascending AI power
- 0.25–0.5 TOPS · AIE1M-AEN · E1M-AEN
Always-on AI at sub-1 mW. Cortex-M55 + Ethos-U55 scaling from 250 GOPS (E3/E5/E7) up to 500 GOPS (E4/E6/E8) for wake-word, vibration anomaly, and ultra-low-power sensing.
35 × 35 mmView detail → - 0.5 TOPS · AIE1M-N93 · E1M-N93 Coming soon
Industrial real-time AI on i.MX 93. 500 GOPS NPU + dual Cortex-A55 + Cortex-M33 in 35 × 35 mm.
35 × 35 mmLearn more → - 4 TOPS · AIE1M-X · E1M-X V2N
Quad-core A55 with 4 TOPS DRP-AI3 in a 45×65 mm form factor.
45 × 65 mmView detail → - 8 TOPS · AIE1M-X · E1M-X V2H Coming soon
RZ/V2H delivers 80 TOPS sparse / 8 TOPS dense in the same 45×65 mm.
45 × 65 mmLearn more → - 29 TOPS · AIE1M-X · E1M-X V2N+M1
RZ/V2N paired with DeepX DX-M1 for 29 TOPS combined AI in 45×65 mm.
45 × 65 mmView detail → - 33 TOPS · AIE1M-X · E1M-X V2H+M1 Coming soon
V2H plus DX-M1 reaches 33 TOPS dense (105 TOPS sparse) for high-throughput inference at the edge.
45 × 65 mmLearn more →
§ Side-by-side comparison
6 modules · diffs in violet
| spec | E1M-AEN 0.25–0.5 TOPS | E1M-N93 Coming soon 0.5 TOPS | E1M-X V2N 4 TOPS | E1M-X V2H Coming soon 8 TOPS | E1M-X V2N+M1 29 TOPS | E1M-X V2H+M1 Coming soon 33 TOPS |
|---|---|---|---|---|---|---|
| Compute | ||||||
| MCU | 2× Arm Cortex-M55 @ 160–400 MHz | Arm Cortex-M33 @ 250 MHz | Cortex-M33 @ 200 MHz | Cortex-M33 | Cortex-M33 @ 200 MHz | Cortex-M33 |
| NPU | 2× Arm Ethos-U55 (250 GOPS · E3/E5/E7 or 500 GOPS · E4/E6/E8) | Arm Ethos-U65 (500 GOPS @ INT8) | DRP-AI3 4 TOPS (dense), 15 TOPS (sparse) | DRP-AI3 8 TOPS dense / 80 TOPS sparse | DRP-AI3 4 TOPS + DeepX DX-M1 25 TOPS | DRP-AI3 (8 TOPS dense / 80 TOPS sparse) + DeepX DX-M1 (25 TOPS) = 33 TOPS dense combined |
| CPU | — | Dual Arm Cortex-A55 @ 1.7 GHz | Quad Cortex-A55 @ 1.8 GHz | Quad Cortex-A55 + 2× Cortex-R8 @ 800 MHz | Quad Cortex-A55 @ 1.8 GHz | Quad Cortex-A55 + 2× Cortex-R8 @ 800 MHz |
| Memory | ||||||
| RAM | 13.5 MB SRAM on-chip | 2 GB LPDDR4 (16-bit) | up to 8 GB LPDDR4X | 8 GB LPDDR4X | up to 8 GB LPDDR4X | 16 GB LPDDR5 |
| ROM | 5.5 MB Flash on-chip | 32 GB eMMC | up to 16 GB eMMC | 64 GB eMMC | up to 16 GB eMMC | 128 GB eMMC |
| Interfaces | ||||||
| MIPI CSI-2 | 1× 2-lane | 1× 4-lane | 2× 4-lane (up to 8 cameras) | 4× 4-lane | 2× 4-lane (up to 8 cameras) | 4× 4-lane |
| MIPI DSI | 1× 2-lane | 1× (also LVDS / Parallel RGB) | 1× (display out) | — | 1× (display out) | — |
| Ethernet | 1 GbE PHY | 2× 1 GbE TSN | 2× 1 GbE | 2× 1 GbE | 2× 1 GbE | 2× 1 GbE |
| USB | USB 2.0 HS | USB 2.0 + USB 3.0 | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 |
| CAN-FD | 1 channel | 1 channel | 2 channels | 2 channels | 2 channels | 2 channels |
| Connectivity | Wi-Fi 6 + BLE 5 | — | Wi-Fi 6 + Bluetooth 5 | — | Wi-Fi 6 / Bluetooth 5 (up to 143 Mbps) | — |
| Video | ISP + JPEG encoder built-in | — | H.264/H.265 hardware encode/decode | — | H.264/H.265 4K encode/decode | — |
| PCIe | — | — | Gen3 x2 | Gen4 x4 | Gen3 x2 | Gen4 x4 |
| Mechanical | ||||||
| Dimensions | 35 × 35 mm | 35 × 35 mm | 45 × 65 mm | 45 × 65 mm | 45 × 65 mm | 45 × 65 mm |
| Pad count | 312 | 312 | 496 | 496 | 496 | 496 |
| Weight | — | — | ~ 18 g | ~ 22 g | ~ 20 g | ~ 24 g |
| Environment | ||||||
| Operating | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C |
§ Roadmap
What's shipping, what's next.
Public roadmap. No vapor — only modules with a defined silicon stack appear in "In development". The horizon column is open invitations rather than dated commitments.
Shipping
In productionOrder today · production-ready
- 0.25–0.5 TOPS
E1M-AEN
Always-on AI at sub-1 mW. Cortex-M55 + Ethos-U55 scaling from 250 GOPS (E3/E5/E7) up to 500 GOPS (E4/E6/E8) for wake-word, vibration anomaly, and ultra-low-power sensing.
- 4 TOPS
E1M-X V2N
Quad-core A55 with 4 TOPS DRP-AI3 in a 45×65 mm form factor.
- 29 TOPS
E1M-X V2N+M1
RZ/V2N paired with DeepX DX-M1 for 29 TOPS combined AI in 45×65 mm.
In development
Sampling 2026Engineering samples · sign up early
- 0.5 TOPS
E1M-N93
Industrial real-time AI on i.MX 93. 500 GOPS NPU + dual Cortex-A55 + Cortex-M33 in 35 × 35 mm.
- 8 TOPS
E1M-X V2H
RZ/V2H delivers 80 TOPS sparse / 8 TOPS dense in the same 45×65 mm.
- 4–33 TOPS
Smart Eye Camera
Industrial Edge-AI Camera powered by the E1M-X V2N+M1 SoM. A lightweight, all-in-one smart vision device delivering high-performance, low-power AI processing for manufacturing, robotics, warehouse automation, and workplace safety — inside a compact, rugged IP67 housing. Configurable from 4 to 33 TOPS by swapping the underlying SoM (V2N / V2H / V2N+M1 / V2H+M1).
- 33 TOPS
E1M-X V2H+M1
V2H plus DX-M1 reaches 33 TOPS dense (105 TOPS sparse) for high-throughput inference at the edge.
On the horizon
ExploringWhat's next on the standard
-
Custom SoM, your silicon
Bring your own SoC — we route it onto the E1M / E1M-X pinout and you ride the SDK + ecosystem.
-
Additional reference SoMs
Conformance tests, plus reference SoMs from new silicon partners as the standard expands.
-
Carrier-board reference designs
Open-source carrier templates so customers can spin their own production boards in weeks, not months.