§ Products
AI compute, scalable.
From 250–454 GOPS always-on sensing to 33 TOPS heterogeneous compute — same unified Alp SDK, same C/C++ API, same toolchain. Pick the AI power you need today; when you scale, code written against the SDK API carries over, and modules within a footprint swap on the same carrier.
§ AI compute ladder
log scale · TOPS
range
250–454 GOPS→33 TOPS
- 250–454GOPSE1M-AEN35 × 35 mm
- 4TOPSE1M-X V2N45 × 65 mm
- 8TOPSE1M-X V2HIn development45 × 65 mm
- 29TOPSE1M-X V2N-M145 × 65 mm
- 33TOPSE1M-X V2H-M1In development45 × 65 mm
§ All modules · ascending AI power
- 250–454GOPS · AIE1M-AEN·E1M-AEN
Sub-1 mW standby with wake-on-event AI. Cortex-M55 + Ethos-U55 (plus Ethos-U85 on E4/E6/E8) scaling from 250 GOPS (E3/E5/E7) up to 454 GOPS (E4/E6/E8) for wake-word, vibration anomaly, and ultra-low-power sensing.
35 × 35 mmView detail → - 4TOPS · AIE1M-X·E1M-X V2N
Quad-core A55 with 4 TOPS DRP-AI3 in a 45×65 mm form factor. Shipping now.
45 × 65 mmView detail → - 8TOPS · AIE1M-X·E1M-X V2HIn development
Target: RZ/V2H with DRP-AI3 at 8 TOPS dense / 80 TOPS sparse in the same 45×65 mm footprint.
45 × 65 mmLearn more → - 29TOPS · AIE1M-X·E1M-X V2N-M1
RZ/V2N paired with DeepX DX-M1 for 29 TOPS combined AI in 45×65 mm. Shipping now.
45 × 65 mmView detail → - 33TOPS · AIE1M-X·E1M-X V2H-M1In development
Target: V2H plus DX-M1 for 33 TOPS dense (8 DRP-AI3 + 25 DX-M1) in the same 45×65 mm footprint.
45 × 65 mmLearn more →
§ Side-by-side comparison
5 modules · diffs in violet
| spec | E1M-AEN 250–454 GOPS | E1M-X V2N 4 TOPS | E1M-X V2HIn development 8 TOPS | E1M-X V2N-M1 29 TOPS | E1M-X V2H-M1In development 33 TOPS |
|---|---|---|---|---|---|
| Compute | |||||
| MCU (SoC) | 2× Arm Cortex-M55: 1× 160 MHz (HE) + 1× 400 MHz (HP) | Cortex-M33 @ 200 MHz | Cortex-M33 | Cortex-M33 @ 200 MHz | Cortex-M33 |
| CPU | 0 / 1 / 2× Arm Cortex-A32 @ 800 MHz (per SoC: E3/E4 none, E5/E6 single, E7/E8 dual) | Quad Cortex-A55 @ 1.8 GHz | Quad Cortex-A55 + 2× Cortex-R8 @ 800 MHz | Quad Cortex-A55 @ 1.8 GHz | Quad Cortex-A55 + 2× Cortex-R8 @ 800 MHz |
| NPU | 2× Arm Ethos-U55; E4/E6/E8 add 1× Arm Ethos-U85 (250 GOPS · E3/E5/E7, 454 GOPS · E4/E6/E8) | DRP-AI3 4 TOPS (dense), 15 TOPS (sparse) | 8 TOPS dense / 80 TOPS sparse (DRP-AI3) | DRP-AI3 4 TOPS + DeepX DX-M1 25 TOPS | 33 TOPS dense (8 DRP-AI3 + 25 DX-M1) |
| MCU (I/O) | — | Cortex-M33 @ 216 MHz — standalone, not in the SoC | Cortex-M33 @ 216 MHz — standalone, not in the SoC | Cortex-M33 @ 216 MHz — standalone, not in the SoC | Cortex-M33 @ 216 MHz — standalone, not in the SoC |
| Memory | |||||
| RAM | 13.5 MB (E3/E5/E7) or 9.75 MB (E4/E6/E8) SRAM on-die | up to 8 GB LPDDR4X | LPDDR4X (capacity TBD) | up to 8 GB LPDDR4X | LPDDR4X (capacity TBD) |
| ROM | 5.5 MB MRAM on-chip | up to 16 GB eMMC | eMMC (TBD) | up to 16 GB eMMC | eMMC (TBD) |
| Interfaces | |||||
| MIPI CSI-2 | 1× 2-lane | 2× 4-lane; up to 8 cameras via MIPI virtual channels (4 per port) with an aggregator / deserializer on the carrier | 4× 4-lane | 2× 4-lane; up to 8 cameras via MIPI virtual channels (4 per port) with an aggregator / deserializer on the carrier | 4× 4-lane |
| MIPI DSI | 1× 2-lane | 1× (display out) | — | 1× (display out) | — |
| Ethernet | 100 Mbps PHY | 2× 1 GbE | 2× 1 GbE | 2× 1 GbE | 2× 1 GbE |
| USB | USB 2.0 HS | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 | USB 3.2 + USB 2.0 |
| CAN-FD | 1 channel (CAN PHY is an assembly option) | 2 channels | 2 channels | 2 channels | 2 channels |
| Connectivity | 2.4 GHz Wi-Fi 6 + BLE 5.4 (BDE-BW3501N, TI CC3501E) | 2.4 / 5 / 6 GHz Wi-Fi (802.11 a/b/g/n/ac/ax, 143 Mbps) + Bluetooth 5.4 (BR/EDR/LE, 3 Mbps) | — | 2.4 / 5 / 6 GHz Wi-Fi (802.11 a/b/g/n/ac/ax, 143 Mbps) + Bluetooth 5.4 (BR/EDR/LE, 3 Mbps) | — |
| Video | ISP + JPEG encoder on E4 / E6 / E8 only (E1M-AEN401 / 601 / 801 / 803) | H.264 1080p60 / H.265 4K (3840 × 2160) 30 fps encode/decode | — | H.264 1080p60 / H.265 4K (3840 × 2160) 30 fps encode/decode | — |
| PCIe | — | Gen3 x2 | Gen3 (4-lane) | Gen3 x2, multiplexed between the on-module DX-M1 (default) and the carrier PCIE0 pads | Gen3 (4-lane) |
| Mechanical | |||||
| Dimensions | 35 × 35 mm | 45 × 65 mm | 45 × 65 mm | 45 × 65 mm | 45 × 65 mm |
| Pad count | 312 | 496 | 496 | 496 | 496 |
| Weight | — | TBD | TBD | TBD | TBD |
| Environment | |||||
| Operating | −40 °C to +75 °C | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C | −40 °C to +85 °C |
§ Roadmap
What's shipping, what's next.
Public roadmap. No vapor — only modules with a defined silicon stack appear in "In development". The horizon column is open invitations rather than dated commitments.
Shipping
ShippingOrder today
- 250–454 GOPS
E1M-AEN
Sub-1 mW standby with wake-on-event AI. Cortex-M55 + Ethos-U55 (plus Ethos-U85 on E4/E6/E8) scaling from 250 GOPS (E3/E5/E7) up to 454 GOPS (E4/E6/E8) for wake-word, vibration anomaly, and ultra-low-power sensing.
- 4 TOPS
E1M-X V2N
Quad-core A55 with 4 TOPS DRP-AI3 in a 45×65 mm form factor. Shipping now.
- 29 TOPS
E1M-X V2N-M1
RZ/V2N paired with DeepX DX-M1 for 29 TOPS combined AI in 45×65 mm. Shipping now.
In development
In developmentTarget specifications · register for updates
On the horizon
ExploringWhat's next on the standard
Custom SoM, your silicon
Bring your own SoC — we route it onto the E1M / E1M-X pinout and you ride the SDK + ecosystem.
Additional reference SoMs
Conformance tests, plus reference SoMs from new silicon partners as the standard expands.
Carrier-board reference designs
Open-source carrier templates so customers can spin their own production boards in weeks, not months.