E1M-X · variant
In developmentE1M-X V2H-M1
Target: V2H plus DX-M1 for 33 TOPS dense (8 DRP-AI3 + 25 DX-M1) in the same 45×65 mm footprint.
In development. Figures below are target specifications; final figures follow on silicon.
E1M-X module shown (V2N-M1), not a E1M-X V2H-M1 photo
In partnership with
§ Target specifications
Design targets for a module in development, not measured or final figures. They can change before the module ships.
compute
- CPU
- Quad Cortex-A55 + 2× Cortex-R8 @ 800 MHz
- MCU (SoC)
- Cortex-M33
- MCU (I/O)
- Cortex-M33 @ 216 MHz — standalone, not in the SoC
- NPU
- 33 TOPS dense (8 DRP-AI3 + 25 DX-M1)
memory
- RAM
- LPDDR4X (capacity TBD)
- ROM
- eMMC (TBD)
interfaces
- MIPI CSI-2
- 4× 4-lane
- PCIe
- Gen3 (4-lane)
- USB
- USB 3.2 + USB 2.0
- Ethernet
- 2× 1 GbE
- CAN-FD
- 2 channels
mechanical
- Dimensions
- 45 × 65 mm
- Pad count
- 496
- Weight
- TBD
environment
- Operating
- −40 °C to +85 °C
§ What you'll get at launch
· Full specs + benchmarks
Final compute, memory, and interface numbers — measured on production silicon, not target estimates.
· Datasheet + HRM
Production-grade datasheet, hardware reference manual, and pinout JSON. One-click download.
· Order & availability
SKU, package, MOQ, lead time, and distributor links published when the module ships.
· Reference designs + SDK examples
Working examples on the unified Alp SDK. Same C/C++ API as the shipping variants.
§ Where it fits in the lineup
AI compute ladder · log scale · TOPS
range
250–454 GOPS→33 TOPS
- 250–454GOPSE1M-AEN35 × 35 mm
- 4TOPSE1M-X V2N45 × 65 mm
- 8TOPSE1M-X V2HIn development45 × 65 mm
- 29TOPSE1M-X V2N-M145 × 65 mm
- 33TOPSE1M-X V2H-M1In development45 × 65 mm